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The following page content corresponds to the products formerly marketed by NEC Electronics

Products > Digital AV LSI > MPEG Decoder
for STB > MPEG4(H.264) >

EMMA3SL/P (µPD61320 - µPD61321)


Overview Target System Product Specification Block Diagram


Overview

µPD6132x

EMMA3SL/P(µPD6132x) is an image-processing LSI chip that integrates in a single chip the functions required for receiving digital broadcasting, such as demultiplexers, decode functions for digital video and audio signals, and image display functions.

In addition to support for the H.264 HD standard, EMMA3SL/P(uPD6132x) has multi-format video support for IP TV STBs and China's AVS standard. It also has integrated enhanced security features. This device is ideal for H.264 pay TV STBs in Asia and Europe.


Target System

  • H.264 STBs
  • Systems with advanced security features
  • Hybrid STB

Product Specification

Product Specification
On-chip CPU
  • Dual CPU with 990MIPS
  • Main CPU:
    • MIPS32® 4KEc® core
    • 495MIPS@324MHz
    • 16 KB instruction cache; 16 KB data cache
  • Sub-CPU
    • MIPS32® 4KEc® core
    • 495MIPS@324MHz
    • 8 KB instruction cache; 8 KB data cache
Memory Interface
  • DDR2 memory interface
    • 16-, 32-bit bus
    • 64 to 256 MB total memory
    • 3.2 GB/s bandwidth
  • Flash ROM interface
    • Up to 64 MB capacity
    • 8-, 16-bit bus
    • Serial Flash Memory
MPEG Transport Stream Processing Engine
  • Stream I/F: Two inputs out of two parallel inputs and two serial inputs
  • MPEG2 TS
  • 108 PID filters
  • 96 section filters
MPEG Video Decoder
  • Support Format
    • MPEG-2 MP@ML, MP@H-14, MP@HL
    • MPEG-4 ASP@L5
    • H.264/AVC HP@L4.0
    • AVS JP@L6.0
    • VC-1 AP@L3
    • DivX® Home Theater@6.x, HD1080p@6.x
    • WMV9
Audio Controller
  • Support Format
    • MPEG-1/2 L1/2, MPEG-4 AAC, MPEG4 HE-AAC, DD, DD+, MP3, WMA
  • SPDIF output
  • PDM output
  • I2S output
  • HDMI output
  • Transcode function from HE-AAC to DTS or DD
Graphics and Display Engine
  • 2D Bit BLT
  • Six graphics planes
  • 1080P video output
  • 256-level alpha-blending function
  • 1/4-4x real-time scalar x 2
  • Easy de-interlace function
Video Encoder
  • 6-channel DAC for simultaneous analog CVBS, YC, and RGB/YCbCr output
  • HDMI output
  • NTSC/PAL/SECAM
USB2.0 Host Controller
  • USB2.0 Interface x2
  • Compliant with EHCI specification
  • High (480 Mbps), full (12 Mbps), and low speeds (1.5 Mbps)
Ethernet Interface
  • Integrated Ethernet MAC conforming to IEEE 802.3/3u/3x
  • Compliant with RMII (10 Mbps/100 Mbps Ethernet) specification
HDMI Interface
  • HDMI 1.3a with X.V. color™
  • HDCP 1.3
Peripherals
  • Two-channel FUART
  • Two-channel SmartCard interface
  • Two-channel I2C interface
  • Two-channel IR receiver
Package
  • 484-pin plastic BGA


Block Diagram

Block Diagram



This device is protected by U.S. patent numbers 5,583,936; 6,516,132; 6,836,549; and 7,050,698, and other intellectual property rights. The use of Macrovision's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited.
This Device can only be sold or distributed to Authorized Buyers.


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